uhm.. it's actually mapped into $de02 on the RR.
But it should be fairly simple.. Don't quite see how Schema would do it using a 74138, though?
Now, /IO1 from C64 means $de00-$deff, so this saves you a lot of logic.
The addresses you'd want mapped in are $de02-$de0f - You wouldn't want $de00/01 since that would effectively make you incabable of using RR or MMC64 at the same time as your new "custom" clock port. You would also have to eliminate mirrors of your clock port anywhere else in memory.
So in order to map in ONLY $de02-$de0f you would need to consider /IO1 and A1-A7 inclusive. The logic for that would be something like:
R = /IO1 & (A1 | A2 | A3) & !(A4 | A5 | A6 | A7)
... i think
The clock port has two chip select signals which is pretty nice.
Connect /IO1 -> /RTC_CS
Connect A1-A3 through an OR gate and put that output to input 1 of a NAND gate.
Connect A4-A7 through an OR gate, invert that output and put it to input 2 of the same NAND gate.
Connect the output of that NAND gate to /SPARE_CS on your clock-port.
- This should give you the required chip-select functionality.
Then connect R/W from C64 to /IORD and /IOWR and remember to invert it for /IORD.
Finally connect C64:A0-A3 to Clock Port:A0-A3, connect D0-D7 andthe rest of the stuff.
OR gates, NAND gates and Inverters should be pretty simple to construct using diodes for the OR gates and a single 7400 for the two inverters and the NAND gate. Don't quite know how all this would work timing-wise with the C64 though.. but a couple of gates shouldn't cause problems..
I haven't tried it, but it sounds like that should be doable
..maybe I'll just go draw up a diagram of that...