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PostPosted: Mon Jul 16, 2007 4:00 pm 
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grue wrote:
I drew up something on myself already too. Now I'm wondering if those cs-signals on clockport are active low or high?

On c64 Reset is active low, is it so on clockport too?


Yes, all signals are active low, except the A and D bus of course.

I guess I kind of forgot about ø2, though ;-) ..and I did some digging into the /IORD and /IOWR signals. These are apparently strobe signals, which means that the clock-port device will read/write the databus on the negative to positive transition.
So for proper R/W to /IORD and /IOWR mapping, I guess you could AND R/W and ø2 together and invert the output to generate a valid /IORD signal. To generate a valid /IOWR you would do the same, but invert the R/W input. ..I'm not completely sure about this, though.. it all depends on the timing.

I already started cooking up some schematics, but there'll be quite a bit of logic involed if you want to mount it internally and at the same time make it "compatible" with any externally mounted cartridge.. severing the /IO1 pin and routing it through this internal clock-port adapter could solve those issues, though.... I guess ;-)
Maybe I should just make an External Clock-Port adapter to start with...


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PostPosted: Mon Jul 16, 2007 8:50 pm 
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Devia wrote:
But it should be fairly simple.. Don't quite see how Schema would do it using a 74138, though?


Sorry about the lack of updates. dW aka Adrian Gonzales actually did the design several months ago. We gave up on it because it wasn't going to work mechanically (the RR-Net would always stick out too far to be useful) or financially (might as well design a lone RR-net compatible cartridge, like 8bits has done).

Here's Adrian's layout (I didn't get a schematic).

Image


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PostPosted: Tue Jul 17, 2007 10:40 am 
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Uhm.. a bit hard to follow that one ;-) ..but designing a clock-port adapter in it's simplest form sounds pretty easy. I was just instantly thinking internally mounted and super compatible :)

I guess it would be something like this:

Image

- which is easily constructable using only one 7400.

Can someone verify if this read/write stuff would work?


Last edited by Devia on Fri Sep 21, 2007 4:24 pm, edited 1 time in total.

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PostPosted: Tue Jul 17, 2007 1:29 pm 
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Atleast to make it work with ide64 some address decoding magic needs to be added to make it just active on a0-a4, if a5-7 is active then it must be mapped out.

as $de20-> $deff is used for ide64 registers

http://www.ide64.org/ide-faq.html#2.2

it would just need some more or/and gates :)


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PostPosted: Tue Jul 17, 2007 3:27 pm 
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What is ic 2 ?

Have Fun

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PostPosted: Tue Jul 17, 2007 4:09 pm 
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zap wrote:
What is ic 2 ?

It's a place to put an 8K ROM, in case you wanted to have something auto-start when the C64 powered up. (not needed in my opinion)


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PostPosted: Wed Jul 18, 2007 2:36 am 
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Schema wrote:
zap wrote:
What is ic 2 ?

It's a place to put an 8K ROM, in case you wanted to have something auto-start when the C64 powered up. (not needed in my opinion)


So would there be a way of loading your configuration into your rrnet using a small program installed into this rom with your ip settings etc.

Has this cart been manufactured.

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PostPosted: Wed Jul 18, 2007 9:00 pm 
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No, it would be a simple read-only 8K EPROM at $8000 (32768) on the C64.

No, none were manufactured. Like I said, too expensive and doesn't solve the RR-Net mechanical fragility.


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PostPosted: Sat Jul 21, 2007 6:49 pm 
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http://picasaweb.google.com/grue74/Ide6 ... 3489373058

looks terrible and it doesnt work :D

I used this as refence http://ide64.org/shrt_bus.txt and connected chip select on rr-net clockport to /CSEL0 signal, also inverted R/W signal for /IORD but it doesnt work..

Any idea is this devias design on R/W signal nand with PHI2 really necessary?

// Grue


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PostPosted: Sun Jul 22, 2007 8:44 pm 
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ok... so I took another look at those 6502 timings and researched a little into those IO read/write strobe signals. Not much to find on the last part, though :shock:
Anyways, here's the adapter I actually build and verified this time :lol:

Image

/IORD low tells rr-net to start sending data onto the databus. When you set it high again, rr-net stops putting data onto the bus.
/IORD must go low when /IO1 is low and R/W is high. PHI2 doesn't matter here.

/IOWR low tells rr-net to get ready to read data off the databus and rr-net will the read the data off the databus when /IOWR goes high again.
/IOWR must go low when /IO1 is low and R/W is low and PHI2 is high

The greatest thing about this, is that I build it into my SX-64 and it fucking works!! no packet loss, no corruption :D ...RR-Net mounted on either RR or MMC64 does not work properly on my SX, but this little thing does. Ahhh.... finally some network on my SX ;-)


Last edited by Devia on Fri Sep 21, 2007 3:32 pm, edited 1 time in total.

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PostPosted: Sun Jul 22, 2007 9:42 pm 
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I got mine working too today with help from tnt, he suggested I'd use 74hc138 and so I did :)

I connected to 3 inputs from ide64 shortbus:

1 = csel0 ($de00-de0f)
2 = r/w
3 = phi2

and enabled outputs permanently

and for IORD I used pin 9 on the chip
for IOWR pin 11

chipselect I connected like in retro replay clockport, spare_cs to gns and rtc_cs to +5v

and it works nicely with ide64!


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PostPosted: Sun Jul 22, 2007 11:29 pm 
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ok, so you only have /IORD asserted during the PHI2 positive period? Looking at the timing diagrams for 6502, I also figured that this should be possible, but no luck here. The timing in the SX however is a bit different, so maybe my first attempt would work in a regular c64 afterall.

Anyways, this wonderful nice little thing is working just perfectly now :D

Image


Now all it needs is a bit more logic to make it work when RR and/or MMC64 is inserted :wink:


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PostPosted: Mon Jul 23, 2007 9:20 am 
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Devia wrote:
ok, so you only have /IORD asserted during the PHI2 positive period? Looking at the timing diagrams for 6502, I also figured that this should be possible, but no luck here. The timing in the SX however is a bit different, so maybe my first attempt would work in a regular c64 afterall.


Yes, its only active on PHI2 positive, I used 74HC series chip as it was only available at the moment, maybe your chip you used was just too slow?

btw, which program you use to draw those fancy schematics?


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PostPosted: Tue Jul 24, 2007 12:08 am 
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My chip was slower, yes.. but I think the problem is actually the falling edge of PHI2 which comes too fast... but well.. that's solved now ;-)

Regarding the software I used.. well, back in the day I used OrCAD, but that's a looooong time ago.. So I figured I'd try some new free stuff out. For the two schematics I posted here, I have used some crappy program called ExpessSCH ..but I wouldn't recommend it.. it's a bit too simple. It includes the ExpressPCB layout software though, so for a small free Capture/Layout package, it might be worth a look.
I also tried out TinyCAD, which seems a bit more advanced, but I'm still evaluating ;-) - Anyways, if you check that out, don't forget to check out FreePCBtoo for PCB layout.


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PostPosted: Tue Jul 24, 2007 4:42 am 
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Devia wrote:
ok, so you only have /IORD asserted during the PHI2 positive period? Looking at the timing diagrams for 6502, I also figured that this should be possible, but no luck here. The timing in the SX however is a bit different, so maybe my first attempt would work in a regular c64 afterall.

Anyways, this wonderful nice little thing is working just perfectly now :D

Image


Now all it needs is a bit more logic to make it work when RR and/or MMC64 is inserted :wink:


Yes a perfect example of the ugly method.
Many time's my poor c64 looked like that.
Good to see :-)

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