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PostPosted: Fri Jun 30, 2006 4:16 pm 
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So, I was wondering how the actual physical implementation of the Clock Port for Retro Replay and MMC64 was done. Since I haven't seen any schematics of the hardware anywhere and so far have been too lazy to actually do a physical inspection of the PCBs, I thought I'd ask you guys first. Anybody know about this?
I mean, is the databus on the clock port somehow latched through something else or is it connected directly to the C64? ..and what about the address bus and other signals?

The reason for asking this is that I want to be able to build a switch of some kind that can switch the RR-Net between MMC64 and RR.


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PostPosted: Fri Jun 30, 2006 4:40 pm 
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I asked the same topic on comp.sys.cbm last week.
Here's the thread.

Unfortunately I didn't get many details. I'm interested in desiging a cartridge with nothing but a clock port on it.


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PostPosted: Sun Jul 02, 2006 4:23 pm 
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I would, just as Groepaz said, begin with studying the Amiga implementation of the clockport, as it has been existing there for some 10+ years.

I would love to make an internal clockport so the RR-net could be completely built in and fittet to the C64 case with just the RJ-45 connector coming out.


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PostPosted: Sun Jul 23, 2006 1:43 am 
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So I did a little digging...

On the MMC64 the implementation is like the following:

Code:

                  CLOCK PORT

                   +--+--+
         GND       | 1| 2|   VCC (+5V)
                   +--+--+
         /INT      | 3| 4|   /SPARE_CS
                   +--+--+
         /RTC_CS   | 5| 6|   /PWR_BAD
                   +--+--+
         /IORD     | 7| 8|   /IOWR
                   +--+--+
         A3        | 9|10|   A2
                   +--+--+
         A1        |11|12|   A0
                   +--+--+
         D7        |13|14|   D6
                   +--+--+
         D5        |15|16|   D4
                   +--+--+
         D3        |17|18|   D2
                   +--+--+
         D1        |19|20|   D0
                   +--+--+
         GND       |21|22|   /RESET
                   +--+--+



Connection to Expansion Port
----------------------------


  Clock Port Signal   |   Expansion Port Signal
-----------------------------------------------------
            GND      <=>  GND (22 and Z, not 1 and A)
            VCC      <=>  +5V (2 and 3)
            /INT     <=>  /NMI
            A0-A3    <=>  A0-A3
            D0-D7    <=>  D0-D7
            /RESET   <=>  /RESET




Why the GND levels are not the same for 22, Z and 1, A beats me.
I haven't checked if that's also the case with RR.

So in other words, the /SPARE_CS, /RTC_CS, /PWR_BAD, /IORD and /IOWR are the ones to pay attention to as all other signals are passed staight through.

So, a pure clock port cart would require a bit of logic too.


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PostPosted: Wed Jul 26, 2006 2:15 am 
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Interesting! I'm not very acquaintant with the 74xx family, but I'm sure there's somebody here on the forum to guide us :)


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PostPosted: Tue Sep 26, 2006 10:08 pm 
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I have a question which fits in this thread:

I have a C64 equipped with MMC64 and RR. My Silversurfer is connected to the clockport of the RR.

When I start a program from MMC which wants to access the clockport at $de08, the device connected to the RR will not be found.

I think the reason is that MMC64's clockport will be acessed instead of RR's clockport.

So how do I make my programms access RR's clockport when running from MMC64?

CU
Kratznagel


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PostPosted: Tue Sep 26, 2006 11:27 pm 
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lda $df11; ora #$09; sta $df11

Bits 0&5 enable cartridge in the passthrough connector, bit3 moves MMC64 clockport to $df20.


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PostPosted: Wed Sep 27, 2006 12:15 am 
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TNX! You saved the day again. :D

CU
Kratznagel


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PostPosted: Wed Sep 27, 2006 12:24 pm 
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If I just had added that missing "and #$df" to clear bit 5... I myself just stuff #$0f into $df11 without thinking - it's unlikely that there are other programs using MMC64 at the same time :)


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PostPosted: Thu Oct 05, 2006 1:35 am 
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Hmm.. there should be a push for this in any future (!) documentation regarding RR-net programming IMHO. Who wants to write it? :D


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PostPosted: Thu Oct 12, 2006 7:05 pm 
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We now have an early design of the "nothing but a clock port" cartridge, so you can hook the RR-Net directly to the 64 if you want. A 74ls138 is the logic chip. I'll post details and a schematic once we get everything finalized.


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PostPosted: Thu Oct 12, 2006 10:28 pm 
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This is good news! It's a great way allowing people access to new peripherals without being forced to buy RR or MMC64. This grants easy access for 'ordinary' users. I'm surprised we haven't seen this from Individual Computers or Protovision yet as I'm sure it would be a great seller itself, and boost sales for RR-net and such. And I don't think RR and MMC64 would suffer sales-wise since they are mainly bought and used by developers, who would buy them anyway...

Keep us posted :!:


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PostPosted: Sun Jul 15, 2007 4:12 pm 
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Did anything ever come out of this?

I'd really like to have rr-net integrated into my c64/c128 so I could free my module port for ide64 :)

So, is clockport just 4xaddress lines + 8xdata mapped into $de08?
I guess also r/w is needed, anything else?


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PostPosted: Sun Jul 15, 2007 11:59 pm 
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uhm.. it's actually mapped into $de02 on the RR.

But it should be fairly simple.. Don't quite see how Schema would do it using a 74138, though?

Now, /IO1 from C64 means $de00-$deff, so this saves you a lot of logic.
The addresses you'd want mapped in are $de02-$de0f - You wouldn't want $de00/01 since that would effectively make you incabable of using RR or MMC64 at the same time as your new "custom" clock port. You would also have to eliminate mirrors of your clock port anywhere else in memory.

So in order to map in ONLY $de02-$de0f you would need to consider /IO1 and A1-A7 inclusive. The logic for that would be something like:
R = /IO1 & (A1 | A2 | A3) & !(A4 | A5 | A6 | A7)
... i think ;-)

The clock port has two chip select signals which is pretty nice.

Connect /IO1 -> /RTC_CS
Connect A1-A3 through an OR gate and put that output to input 1 of a NAND gate.
Connect A4-A7 through an OR gate, invert that output and put it to input 2 of the same NAND gate.
Connect the output of that NAND gate to /SPARE_CS on your clock-port.
- This should give you the required chip-select functionality.
Then connect R/W from C64 to /IORD and /IOWR and remember to invert it for /IORD.

Finally connect C64:A0-A3 to Clock Port:A0-A3, connect D0-D7 andthe rest of the stuff.

OR gates, NAND gates and Inverters should be pretty simple to construct using diodes for the OR gates and a single 7400 for the two inverters and the NAND gate. Don't quite know how all this would work timing-wise with the C64 though.. but a couple of gates shouldn't cause problems..

I haven't tried it, but it sounds like that should be doable ;-)

..maybe I'll just go draw up a diagram of that...


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PostPosted: Mon Jul 16, 2007 2:18 pm 
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I drew up something on myself already too. Now I'm wondering if those cs-signals on clockport are active low or high?

On c64 Reset is active low, is it so on clockport too?


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